1. Field of the Invention
This invention relates to video signal processing circuits and, more particularly, to such a circuit which operates to improve the quality of a video signal by producing an interpolated scan line intermediate successive main scan lines normally present in a received video signal; and also by modifying the main scan line signals themselves.
2. Description of the Prior Art
Conventional television signals such as NTSC signals, normally are transmitted as so-called interlaced signals which, when reproduced on a conventional television receiver, produce a video picture formed of interlaced scan lines. The frame which constitutes one complete video picture actually is comprised of two successive interlaced fields. The first field consists of odd horizontal lines, such as lines numbered 1, 3, 5, etc., and the next succeeding field consists of the even numbered lines, that is, lines numbered 2, 4, 6, and so on. As is conventional, when the odd field of video signals is received by a conventional television receiver, the odd lines first are displayed; and when the next-following even field is received, the even lines are interlaced between the odd lines to reconstitute the complete video frame.
It is recognized that no even line information is reproduced when an odd field is received and, likewise, no information regarding the picture contents of the odd lines is reproduced when an even field is received. Of course, the inherent remenance of the CRT display tube phosphors provides continued display of the scan lines. Nevertheless, the overall quality of the video picture displayed on a conventional television receiver would be improved if, during each field interval, both odd and even line intervals are displayed. Stated otherwise, the quality of the video picture would be improved if, during a field interval, 525 lines rather than the usual 262 (or 263) lines are displayed.
A proposal to generate so-called interpolated scan lines of video information in response to the actual, main scan lines received in each field is found in NEC Technical Report, Vol. 41, No. 3/1988. A block diagram representing this proposal is set out in FIG. 1 herein. As illustrated, a conventional television signal, such as an NTSC signal, is received at an input terminal 1 and converted from its analog form to digital form by an analog-to-digital (A/D) converter 2. The digitized composite television signal then is separated by a luminance/chrominance (Y/C) separator 3 into its luminance and chrominance components. A typical Y/C separator includes a comb filter and, preferably, is of the so-called movement adaptive type. In addition to the comb filter, Y/C separator 3 may include a spectral filter circuit for separating the relatively lower frequency luminance components from the higher frequency chrominance components. Use of a comb filter generally is preferred to achieve Y/C separation, and its performance may be improved if there is little or no movement in the video scene represented by the video signals supplied thereto. The comb filter and spectral filtering circuitry included in the movement adaptive Y/C separator operate as a function of detected movement in the video scene then being received. Accordingly, Y/C separator 3 is coupled to a movement detector circuit 4 which is a conventional circuit adapted to sense whether movement is present from one scan line to the next. As one example, the movement detector circuit may detect the correlation between successively received horizontal lines.
The separated luminance component Y is supplied to a noise reducing circuit 5Y and, similarly, the separated is chrominance component, after being decoded into color difference signals R-Y and B-Y by a chrominance decoder 6, is supplied to a noise reducing circuit 5C. The color difference signals R-Y and B-Y are supplied to the noise reducing circuit in time division multiplexed form.
Noise reducing circuits 5Y and 5C are conventional and are of the movement adaptive type. Accordingly, these noise reducing circuits are coupled to yet another movement detector 7 which controls the operation of the noise reducing circuits as a function of movement detected in the received video signals.
After noise reduction, the luminance signal is supplied to an interpolating circuit 8Y and, similarly, the noise-reduced time division multiplexed color difference signals are supplied to an interpolating circuit 8C. These interpolating circuits are similar in their function and operate to produce the normal, main scan line signals as well as interpolated scan line signals. Interpolated scan line signals are a relatively accurate approximation of the video information that is expected to be positioned between, for example, successive odd scan lines or successive even scan lines in an odd or even field. Thus, interpolating circuit 8Y generates main scan line luminance signals Y.sub.m and interpolated scan line luminance signals Y.sub.c. Likewise, interpolating circuit 8C generates main scan line chrominance signals R.sub.m -Y.sub.m and B.sub.m -Y.sub.m (that is, time division multiplexed color difference signals) and interpolated scan line chrominance signals R.sub.c -Y.sub.c and B.sub.c -Y.sub.c (which also are in time division multiplexed form). For convenience hereafter, the time division multiplexed color difference signals are represented as R.sub.m -Y.sub.m /B.sub.m -Y.sub.m for the main color difference scan lines signals and as R.sub.c -Y.sub.c /B.sub.c -Y.sub.c for the interpolated color difference scan line signals.
Interpolating circuits 8Y and 8C are of the movement adaptive type and, thus, for proper control thereover, these circuits are coupled to still another movement detector circuit 9. That is, the operation of the interpolating circuits is controlled as a function of detected movement in the video scene represented by the received video signals. Interpolating circuit 8Y generates interpolated scan lines Y.sub.c of luminance information intermediate actual, main scan lines Y.sub.m of luminance information. Likewise interpolating circuit 8C generates interpolated scan lines R.sub.c -Y.sub.c /B.sub.c -Y.sub.c of chrominance information intermediate actual, main scan lines R.sub.m -Y.sub.m /B.sub.m -Y.sub.m of chrominance information.
The main and interpolated luminance and chrominance signals Y.sub.m, Y.sub.c, R.sub.m -Y.sub.m /B.sub.m -Y.sub.m and R.sub.c -Y.sub.c /B.sub.c -Y.sub.c are time compressed. Timebase compressing circuit 10Y is coupled to interpolating circuit 8Y to time compress the main and interpolated scan lines Y.sub.m and Y.sub.c of luminance information. Likewise, timebase compressing circuit 10C is coupled to interpolating circuit 8C to time compress the main and interpolated scan lines of time division multiplexed color difference signals R.sub.m -Y.sub.m /B.sub.m -Y.sub.m and R.sub.c -Y.sub.c /B.sub.c -Y.sub.c.
The purpose of the timebase compressing circuits is to reduce the time period occupied by each main and interpolated scan line to one-half the conventional horizontal period. Thus, in the normal horizontal time interval, two successive scan lines of information are provided: the main scan line and the interpolated scan line. It will be appreciated that this enables the scanning circuitry of a cathode ray tube, such as CRT 18, to scan a main scan line followed by an interpolated line over a time interval normally occupied by a single conventional horizontal line interval.
The time compressed main and interpolated scan lines of luminance information produced by timebase compressing circuit 10Y are converted from digital to analog form by a D/A converter 11Y. Advantageously, timebase compressing circuit 10C functions to demultiplex the time division multiplexed main and interpolated scan lines of color difference signals, thereby separating the red and blue color difference signals which are, in turn, converted to analog form by D/A converters 11R and 11B, respectively. Thus, it is seen that D/A converter 11R receives a time-compressed main scan line of red color difference information R.sub.m -Y.sub.m, followed by an interpolated scan line of red color difference information R.sub.c -Y.sub.c. Likewise, D/A converter 11B receives a time-compressed main scan line of blue color difference information B.sub.m -Y.sub.m, followed by an interpolated scan line of blue color difference information B.sub.c -Y.sub.c. As a consequence, the D/A converters produce main analog scan line signals followed by interpolated analog scan line signals.
A matrix circuit 16 is coupled to D/A converters 11Y, 11R and 11B and operates in a conventional manner to combine the analog luminance and color difference signals to produce red, green and blue (RGB) signals, respectively. These RGB signals may be thought of as so-called "double speed" color signals because each occupies only one-half of a conventional horizontal line period. Such double speed color signals are amplified by amplifiers 17R, 17G and 17B, respectively, and supplied to the respective red, green and blue cathodes of CRT 18. Thus, although the video signals originally received at input terminal 1 are conventional interlaced signals formed of odd and even fields transmitted in succession, interpolating circuits 8Y and 8C, timebase compressing circuits 10Y and 10C and D/A converters 11Y, 11R and 11B, function to produce non-interlaced signals to improve the quality of the displayed video picture.
Of course, the various circuits illustrated and described in FIG. 1 must be supplied with clock signals for proper operation thereof. Clock generators 12 and 13 generate such clock signals for suitable operation of the digital circuits. Each clock generator is synchronized with a different component derived from the received video signal. In the illustrated circuitry, clock generator 12 generates a clock signal CLKC which is phase locked to the color burst signal SC normally included in the received composite video signal. Clock generator 13 generates a clock signal CLKH which is phase locked to the horizontal synchronizing signal HD included in the received video signal. Clock signals CLKC and CLKH are supplied to inputs a and b, respectively, of a selector switch 14 whose operation is controlled by a standard/non-standard identifying circuit 15.
The identifying circuit functions to determine whether the input video signal supplied to terminal 1 is a so-called standard signal or a non-standard signal. An example of a standard signal is a broadcast television signal; and an example of a non-standard signal is a video signal reproduced from a video tape recorder or other video playback device. As one embodiment thereof, identifying circuit 15 detects the chrominance subcarrier frequency f.sub.sc to determine if it is, in fact, equal to 455f.sub.h /2, where f.sub.h is the horizontal repetition frequency. If identifying circuit 15 detects the presence of a standard signal, switch 14 is controlled to supply clock signal CLKC generated by clock generator 12 to the illustrated digital circuits. Alternatively, if identifying circuit 15 detects a non-standard signal, selector switch 14 is changed over to couple clock signal CLKH generated by clock generator 13 to the digital circuits.
For example, let it be assumed that a non-standard signal, such as a video signal reproduced from a VCR, is supplied to input terminal 1. Let it be further assumed that the luminance signal included in this non-standard signal exhibits jitter. Nevertheless, as is conventional in many video tape recorders, the chrominance subcarrier of the reproduced signal is phase-locked by an automatic phase control circuit (APC) to prevent significant color disturbance in the video signal. If the clock signal CLKC, phase-locked to the chrominance subcarrier SC, is supplied to the digital circuits, Y/C separator 3 will operate quite satisfactorily. This is because the phase-locking of the clock signal to the chrominance subcarrier results in coincident samples from one line interval to the next, and this phase coincidence from line to line facilitates the Y/C separating capabilities of a comb filter. However, the existence of jitter in the luminance signal and, thus, in the horizontal synchronizing signal HD, may not be accompanied by identical jitter in the chrominance subcarrier. Consequently, if the clock signal CLKH, synchronized to the horizontal synchronizing signal HD, is used as the clock signal by the Y/C separating circuit, the samples generated during one line interval may not coincide with the samples generated during the next line interval. As a result, such small phase differences in the chrominance samples may impede the cancellation of the chrominance component from one line to the next in the comb filter. Thus, luminance/chrominance separation by the comb filter may not be satisfactory if the clock signal CLKH is used when a non-standard video signal is detected. But, this difficulty encountered by the Y/C separating circuit is contradicted by the improvement achieved in the operation of interpolating circuits 8Y and 8C by using the clock signal CLKH phase-locked to the horizontal synchronizing signal. Thus, when a non-standard signal, such as may be reproduced from a VCR, is present, it is preferred to use the clock signal CLKC to control the Y/C separator and to use the clock signal CLKH to control the interpolating circuits.
Of course, when a standard video signal is present, the luminance signal exhibits no jitter and, therefore, either the clock signal CLKC or the clock signal CLKH may be used by the Y/C separator and by the interpolating circuits. Identifying circuit 15 controls selector switch 14 to select clock signal CLKC or clock signal CLKH as a function of the degree of jitter which may be present in the received video signal.
In the previously proposed interpolating circuit shown in FIG. 1, the Y/C separator, the noise reducing circuits and the interpolating circuits rely on digital memories and on movement detecting circuitry for proper operation. As a result, the overall circuit arrangement is relatively complicated and the circuit architecture may be expected to be quite dense. This is further compounded by the addition of identifying circuit 15 and the change-over switching circuitry used to select clock signals CLKC or CLKH.